With a view to achieving higher integration and higher performance of an LSI device, an SGT (Surrounding Gate Transistor) has been proposed which comprises a pillar-shaped semiconductor layer formed on a surface of a semiconductor substrate, and a gate formed to surround a sidewall of the pillar-shaped semiconductor layer (see the following Patent Document 1). In the SGT, a drain, a gate and a source are arranged in a vertical direction, so that an occupied area can be significantly reduced as compared with a conventional planar transistor.
In cases where a DRAM is formed using an SGT, a memory cell array can be configured as a cross point type, so that a cell size of 4F2 can be achieved, in theory. Thus, it is possible to drastically reduce a cell size, as compared with a conventional planar transistor-based DRAM having a cell size of 6F2 or 8F2. Therefore, a SGT-based DRAM (hereinafter referred to as “SGT-DRAM”) has great potential as a DRAM requiring higher integration as a top priority, and an embedded memory for a CPU requiring an increase in capacity of a memory for caching, etc. However, in actual development toward practical use of an SGT-DRAM, a transistor structure in a peripheral circuit section and a logic circuit section to be embedded is critically important as well as a DRAM cell structure. In such a transistor, there is an extremely strong need for higher transistor performance as well as a reduction in occupied area. The following Non-Patent Document 1 is cited as a conventional example which mentions an SGT-DRAM, including a structure of a peripheral circuit section. This conventional example will be described below.
FIG. 34(a) is a top plan view of a DRAM cell array disclosed in the Non-Patent Document 1, and FIG. 34(b) is a sectional view taken along the cutting-plane line A-A′ in the top plan view of FIG. 34(a).
Referring to the top plan view of FIG. 34(a), a plurality of pillar-shaped silicon layers 704 are formed on respective ones of a plurality of intersecting points of a plurality of bit lines 702 formed on a buried oxide film layer 701 with a plurality of word lines 703 formed above the buried oxide film layer 701, and a plurality of selection transistors are formed based on the respective pillar-shaped silicon layers 704. Further, a capacitor element is formed on a top of each of the selection transistors. A plurality of memory cells are formed at respective ones of all the intersecting points of the bit lines with the word lines, to make up a cross-point type cell array.
Referring to the sectional view of FIG. 34(b), each of the bit lines is formed by an N+ diffusion layer 702 on the buried oxide film layer 701, and each of the word lines is formed by a polysilicon line. Each of the pillar-shaped silicon layers 704 is formed through a process of forming a gate dielectric film and a silicon film inside each of a plurality of contact holes formed in the word lines from thereabove, to make up the selection transistor. The capacitor element on the top of each of the selection transistors is formed by a lower electrode 705, a capacitor dielectric film 706 and an upper electrode 707, in the same manner as that in a conventional stacked-capacitor DRAM.
FIG. 35 is a sectional view showing a CMOS inverter disclosed in the following Non-Patent Document 1, as one example of a peripheral circuit. Referring to the sectional view of FIG. 35, an N+ source diffusion layer 802a and a P+ source diffusion layer 802b are formed on a buried oxide film 801, and a pillar-shaped silicon layer 804a forming an NMOS (NMOS-forming pillar-shaped silicon layer 804a) and a pillar-shaped silicon layer 804b forming a PMOS (PMOS-forming pillar-shaped silicon layer 804b) are formed on the N+ source diffusion layer 802a and the P+ source diffusion layer 802b, respectively. Further, an N+ drain diffusion layer 805a is formed on a top of the NMOS-forming pillar-shaped silicon layer 804a, and a P+ drain diffusion layer 805b is formed on a top of the PMOS-forming pillar-shaped silicon layer 804b. A gate 803 is formed around the respective pillar-shaped silicon layers. The N+ source diffusion layer 802a is connected to a ground potential via a contact extending from a line layer 808a, and the P+ source diffusion layer 802b is connected to a power supply potential via a contact extending from a line layer 808b. Further, the diffusion layer (805a, 805b) on each of the tops of the NMOS and PMOS-forming pillar-shaped silicon layers is connected to an output potential via a contact extending from a line layer 808c. 
In this conventional example, an SOI (silicon-on-insulator) substrate is used to eliminate a need for forming a well, so that the source diffusion layers 802a, 802b can be isolated from each other simply by forming therebetween an element isolation region with a desired width through etching. This makes it possible to reduce a circuit area.
A production method for the CMOS inverter in the above conventional example will further be described based on sectional views of a DRAM cell section. Referring to FIG. 36(a), a silicon layer on a buried oxide film 701 is patterned to form a plurality of bit lines 702. Subsequently, a dielectric film and a polysilicon film are formed. Subsequently, the polysilicon film is patterned to form a plurality of word lines 703 and others. Referring to FIG. 36(b), a dielectric film is further formed, and a plurality of contact holes 708 are formed to penetrate through the polysilicon film and reach the silicon layer. Referring to FIG. 36(c), a surface of the polysilicon film defining each of the contact holes 708 is oxidized to form a gate oxide film, and an amorphous silicon film is formed to fill the respective contact holes 708. Subsequently, an upper diffusion layer 705 is formed in an upper portion of the amorphous silicon film by ion implantation. Referring to FIG. 36(d), the upper diffusion layer 705 is patterned and then a capacitor dielectric film 706 and an upper electrode 707 are formed to form a capacitor element.                Patent Document 1: JP 2-188966A        Non-Patent Document 1: S. Maeda, et al., “Impact of a Vertical Φ-Shape Transistor Cell for 1 Gbit DRAM and Beyond”, IEEE TRANSACTIONS ON ELECTRON DEVICES, December 1995, VOL. 42, NO. 12, pp. 2117-2124        
However, the structure of the peripheral circuit section in the above conventional example has the following problems.
Firstly, in view of high-performance requirements for a transistor in a peripheral circuit section of a DRAM and a logic circuit section of a DRAM-embedded device, it is contemplated to subject a source/drain diffusion layer to silicidation in order to reduce a parasitic resistance. However, in the above conventional example, a silicide layer must be formed in the source diffusion layer before forming a transistor. Generally, a silicide layer is low in thermal resistance. Thus, if a silicide layer is formed in the source diffusion layer and then a heat treatment required for forming a transistor is performed at about 1000° C., a resistivity of the silicide layer will become higher. Therefore, in the above conventional example, it is difficult to form in the source diffusion layer a silicide layer which contributes to a reduction in parasitic resistance.
Secondly, in the above conventional production method, the transistor-forming pillar-shaped silicon layer is made of polysilicon. This causes a significant deterioration in transistor performance, as compared with a conventional transistor where a channel region is made of single-crystal silicon.
As will be appreciated from the above description, the transistor structure of the peripheral circuit section disclosed in the Non-Patent Document 1 has significant difficultly in meeting the high-performance requirements for a transistor in a peripheral circuit section of a DRAM and a logic circuit section of a memory-embedded device.